The present invention relates to microelectronic packaging and more particularly relates to connection components and methods for packaging microelectronic elements such as semiconductor chips, wafers, and other elements.
As illustrated in certain preferred embodiments of U.S. Pat. No. 5,518,964 (“the '964 Patent”) movable interconnections between a microelectronic elements such as a semiconductor chip or wafer and another element can be provided by providing a connection component incorporating a dielectric body and leads extending on the bottom surface of the dielectric body. The leads may have first or fixed ends permanently attached to the dielectric body and connected to electrically conductive features such as terminals, traces or the like on the dielectric body. The leads also may have second or tip ends releasably attached to the dielectric body. The dielectric body, with the leads thereon, may be juxtaposed with the microelectronic element and the second or tip ends of the leads may be bonded to contacts on the microelectronic element. After bonding, the dielectric body and the microelectronic element are moved away from one another, thereby deforming the leads to a vertically extensive disposition. A curable liquid material may be introduced between the dielectric body and the microelectronic element during or after the moving step and cured to form a compliant dielectric layer as, for example, an elastomer or a gel surrounding the leads.
The resulting packaged microelectronic element has terminals on the dielectric body of the connection component which are electrically connected to the contacts on the chip but which can move relative to microelectronic element so as to compensate for thermal effects. For example, a semiconductor chip packaged in this manner may be mounted to a circuit board by solder-bonding the terminals to conductive features of the circuit board. Relative movement between the circuit board and the chip due to thermal effects is taken up in the movable interconnection provided by the leads and the compliant layer. Many variations of these processes and structures are disclosed in the '964 patent and the entire disclosure of such patent is incorporated herein by reference. Merely by way of example, the package-forming process can be conducted on a wafer level, so that numerous semiconductor chips in unitary wafer are connected to connection components in one operation or in one sequence of operations.
Additional variations and improvements of the process taught in the '964 patent are disclosed in commonly assigned U.S. Pat. Nos. 5,578,286; 5,830,782; 5,688,716; and 5,913,109.
A further variant of the process taught in the '964 patent is described in certain embodiments of co-pending, commonly assigned U.S. patent application Ser. No. 09/271,688, filed Mar. 18, 1999. [136 II CIP] In these embodiments, a microelectronic component such as a wafer including one or more semiconductor chips and having contacts on a front surface may be provided with leads by forming the leads in place on the semiconductor element so that the leads overlie the front surface. The formed leads desirably have contact ends connected to the contacts and have tip ends releasably connected to the semiconductor element. The semiconductor element, with the leads thereon, is juxtaposed with a further element such as a support and/or dielectric element having pads thereon. The tip ends of the leads are bonded to the pads. Following the bonding step, the chip or wafer can be moved away from one another so as to bend the leads toward a vertically-extensive disposition. Most preferably, the pads are wider than the ends of the leads connected to the pads. For example, the pads may be in the form of linear features extending transverse to the tip ends of the leads. Where the leads on the chips are aligned to pads wider than the ends of the leads, the process can operate satisfactorily even with a relatively large alignment tolerance between the chip or wafer and the element bearing the pads.
As described in certain preferred embodiments of the co-pending, commonly assigned U.S. Pat. No. 6,117,694; U.S. patent application Ser. No. and 09/317,675, filed May 24, 1999, and U.S. Pat. No. 6,228,686, a connection component may be provided as a sheet of a dielectric material with a main region and with lead regions defined by slots extending through the sheet. Such slots extend partially around each such lead region, so that a tip end of each lead region is movable relative to the main region. Where terminals on the main region of the sheet are connected to one element and the tip ends of the leads are connected to another element, the lead regions can be bent out of the plane of the sheet to form vertically extensive leads by moving the elements away from one another. As described in certain preferred embodiments of U.S. Provisional Application No. 60/204,735 filed May 16, 2000, and the corresponding non-provisional U.S. patent application Ser. No. 09/858,770 filed May 16, 2001, such a sheet can be formed in whole or in part on the surface of a microelectronic element such as a wafer. The disclosures of all of the aforesaid patents and applications are hereby incorporated by reference herein.
Despite these improvements in the art, still further improvements and variations would be desirable.